This invention relates generally to current divider circuitry and more particularly to current divider circuitry suitable for use in digital-to-analog converters.
As is known in the art, many digital-to-analog converters include current divider circuitry to produce a flow of current having a magnitude proportional to a magnitude represented by a digital word fed to such converter. One such current divider circuit includes a resistor ladder network which has a plurality of resistors disposed in shunt and series arms of such network. Generally the resistances of the resistors in the shunt arms are twice as large as the resistances of the resistors in the series arms. This type of ladder network is sometimes referred to as an R-2R ladder network. A voltage source is sometimes coupled to a first one of the shunt and series resistors of the network so that current flows from such voltage source to ground through each one of the shunt resistors with the amount of current flow through each one of the shunt resistors being successively reduced by a factor of 2:1 from the first one of the shunt resistors to the last one of the shunt resistors. Each one of the shunt resistors is connected to a switch which directs the current flowing through the resistor connected to it to ground via a first bus or a second bus selectively in accordance with a control signal fed to the switch. Each bit of the digital word fed to the digital to analog converter is used as the control signal for a corresponding one of the switches, and each switch directs current flowing through the shunt resistor connected to it to ground through either the first bus, as when the control signal fed to such switch represents a logical 1 bit, or the second bus, as when the control signal fed to such switch represents a logical 0 bit. The most significant bit is used as the control signal for the switch connected to the first shunt resistor of the ladder network and the least significant bit is used as the control signal for the switch connected to the last shunt resistor of the ladder network. Consequently, the magnitude of the current flow from the voltage source to ground through the first bus is proportional to the magnitude represented by the digital word fed to the converter.
One type of digital to analog converter which uses the R-2R ladder network includes a pair of field effect transistors for each one of the switches in the shunt arms of the network. The source electrodes of each one of the pair of transistors are connected to a corresponding one of the shunt resistors and the drain electrodes are connected to ground through the first and second buses, respectively. The bits of the digital word are fed to driver circuits to produce "true" and "complement" signals in response to each one of such bits. The "true" and "complement" signals produced in response to each bit are fed as switching signals to the gate electrode field effect transistors in series with a corresponding one of the shunt resistances to place a selected one of the pair of transistors in a conduction condition and the other one of the pair of transistors in a nonconduction condition. Therefore, current flowing through each one of the shunt resistors will be directed to ground through the source and drain electrodes of a selected one of the pair of transistors, such transistor being selected in accordance with the switching signals fed to the pair of transistors. When either one of the pair of transistors is in a conduction condition such transistor has some finite resistance between the source and drain electrodes. Consequently, in order to provide a true R-2R ladder network the conduction resistance of the transistors in successive shunt arms of the ladder network must be successively increased in order to precisely obtain a 2:1 successive reduction in the amount of current flow through the resistors of the ladder network. To put it another way, with such arrangement a successive 2:1 reduction in the current flow through the shunt resistors with the R-2R ladder network is obtained by maintaining the voltage at the terminals connecting the shunt resistors to the pairs of transistors at the same reference voltage. Consequently, if the current passing through one of the pair of transistors in the first shunt arm is twice as large as that current flowing in one of the pair of transistors in the next succeeding shunt arm the conducting resistance of the transistor in the first shunt arm must be half as large as the conducting resistance of the transistor in the next succeeding shunt arm. In this way the voltage drop across each one of the conducting transistors is the same and therefore the voltages at the terminals connecting the shunt resistors to the pairs of transistors are maintained at the same reference potential. That is, for example, if the conduction resistance of each one of the pair of transistors fed by the most significant bit of the digital word is in the order of 20 ohms, the conduction resistances of each one of pair of succeeding transistors must be 40 ohms, 80 ohms, etc.. In order to obtain the successively larger "on" resistances the size of the transistor must be correspondingly increased. It follows then that when such converter is to be formed as an integrated circuit having a fixed amount of surface area on each chip, the number of bits which such converter is able to operate on is limited. That is, for example, if a 12 bit digital to analog converter is desired, while the conduction resistance of each one of the first pair of transistors is, say, 20 ohms, the conduction resistances of each one of the succeeding pairs of transistors will have to be, with such arrangement, successively increased from 40 ohms to 42K ohms, thereby requiring the switching transistors to occupy a significantly large amount of area on the chip. Further, such large transistors have relatively large gate capacitances which increases their switching response time. Still further, since the conducting resistances of such transistors are relatively large, they must be formed with a high degree of accuracy.
One way suggested to obtain a proper 2:1 successive reduction in current flow is to modify the ladder network so that many of the least significant bit responsive transistors have the same conductive resistances but the shunt resistances connected to such transistors are correspondingly increased. With such arrangement, however, because the temperature variation effect on the conductive resistances of the active transistors is not matched to the temperature variation effect on the resistance of the passive shunt resistors, the temperature range of operation of a digital-to-analog converter using such arrangement is limited.